Overview-Semiconductor
The key highlights of our semiconductor practice:
Expertise in implementing complex SoCs / ASICs in 3nm ,4nm,5nm, 7nm,8nm, 10nm, 14nm, 16nm, 28nm, and other older technology nodes
Our customers include the global top 20 semiconductors.
Semiconductor solutions:
Our team is experienced technical experts in all areas, from RTL to GDSII. We have well-established internal processes, methodologies, and workflows to work on any specification or an existing design and execute the complete RTL design, integration, verification, STA-Synthesis, physical design, and DFT to tape out an entire SoC (System on Chip) design.
Our motto is to be a global semiconductor service and solutions provider and help its clients meet market-driven challenges. We work closely with several integrated device manufacturers (IDMs), fabless semiconductor companies, original equipment manufacturers, pure-play foundries, engineering design automation (EDA), and IP vendors to accelerate their products to the market.
Our VLSI design and verification services expertise can transform your product ideas into cost-effective, robust, performance, and area-optimized System-on-Chip (SoC). We cater to the growing demands of the 5G, data center infrastructure, automotive, consumer electronics, and industrial markets.
Overview-Semiconductor
The key highlights of our semiconductor practice:
Expertise in implementing complex SoCs / ASICs in 3nm ,4nm,5nm, 7nm,8nm, 10nm, 14nm, 16nm, 28nm, and other older technology nodes
Our customers include the global top 20 semiconductors.
Semiconductor solutions:
Our team is experienced technical experts in all areas, from RTL to GDSII. We have well-established internal processes, methodologies, and workflows to work on any specification or an existing design and execute the complete RTL design, integration, verification, STA-Synthesis, physical design, and DFT to tape out an entire SoC (System on Chip) design.
Quality and functional integrity are our priorities. To achieve this, we have our processes, project management team, an expert senior core team, and one of the best engineering teams with experience taping out multiple designs.
Ability to tape out a complete SoC (System on Chip)
Comprehensive SoC services: design, plan, and execute the RTL integration, IP and SoC verification, STA and Synthesis, Physical Design, and DFT.
A team of senior technical experts in all the areas from RTL to GDSII.
Well-proven internal workflows and best practices.
Front End Design & Verification
Design
- SoC Architecture and IP Micro Arch
- SoC and Sub-System Integration
- DFT RTL Design and Integration
- RTL Quality Checks
- Synthesis, Timing, Caliber and FEV
- Timing, Constraints and Constraints Validation
Verification
- Environment Architecture Development
- Verification
- SoC Verification
- IP/SS Verification
- DFT/DFD Validation
- Power-aware Verification
- AMS
- CPU Verification
- Gate Level Simulations (GLS)
- VIP Development, 3rd party VIP Integration, Development and Modelling
- Assertions, Coverage and Formal Verification
- Automation and Regression Management
FPGA
- ASIC and IP Prototyping with FPGA
- FPGA and System Architecture Design
- RTL Design from Microarchitecture
- Verification of RTL in UVM/OVM and other Methodology
- Porting to Different FPGA, FPGA to ASIC Porting and Vice Versa
- Board Design and Bring up
- FPGA Fitment, Bitmap Generation
- FPGA/System Validation on Board
- Multi-Million Gates Complex FPGA Design and Validation
Front End Design & Verification Expertise
With a laser-sharp focus on all design parameters, Team I2Lab leaves no stone unturned in Front End Design and Verifications. This helps you get error-free designs in the least turnaround time.
Physical Design & Signoff
Synthesis
- Setting up the Synthesis Flow
- Developing Constraints
- Logic and Physical Aware Synthesis Using Industry Standard Tools
Physical Design (RTL – GDSII)
- RTL Synthesis (Logical & Physical aware)
- Design For test (Scan, MBIST, ATPG)
- Library Quality Checks, IP Validation
- Die Size Estimation (Bump and Ball requirement, MFU)
- IO Planning, Floor Planning, Partitioning
- Power Planning and Low Power Strategy
- Place & Route
- Clock Tree Synthesis
- Design for Manufacture (Metal Fill, Spare Cells, Decap Cells)
- Power Analysis (EM/IR)
- Physical Verification (DRC, LVS, ERC, ANTENNA, PERC, XOR)
- Low Power Checks (CLP) & Formality (LEC)
- Full Chip/Partition Timing Closure, MMMC Signoff
- ECO Iteration (Functional & Timing Fixes)
Static Timing Analysis (STA)
- Setting up the STA flow
- Develop Timing Constraints for Multiple Modes
- Timing Analysis for Multi Modes & Multi Corners
- Timing ECOs using TSO or DMSA
- SI Analysis
Logic Equivalence Check (LEC)
- Setting up the LEC flow for both Functional and CLP
- Block Level and Top Level LEC Runs
- Analysis & Debug skills for Complex Issues
Physical Design Flow
The team I2LAB undergoes a rigorous research and focus the attention to all design aspects. Optimizing the design and other parameters, the turnkey product is delivered after an extensive examination.
Design for Test
DFT Architecture and Implementation
Flow and Methodology Development
Scan Implementation with and without Compression
- Implementation of Hierarchical and Flat Scan for Small and Multi-million Gates Design
- LBIST Implementation and Spyglass at RTL Level
- LEC for Scan Netlist
- IJTAG Implementation at Block and SOC Level
ATPG Pattern Generation for Different Fault Models
- ATPG Pattern Generation for Stuck-at, Transition, Bridging and Cell aware Fault Model and Extensive Coverage Analysis at Block Level and SOC Level
- Low Power Pattern Generation, Pattern Optimization and TPI Analysis
- Pattern Retargeting at SOC Level
Memory Testing using MBIST Implementation
- MBIST Implementation with and without repair
- Simulation and Debug at Timing and No-timing Simulations
IO Testing using JTAG/BSCAN Implementation
- Implementation of Boundary Scan at SOC Level
- Expertise in IEEE1149.1 and IEEE1149.6 Standards
DFT Validation
- Simulations at Timing and No-timing
- DFX Validation at RTL and Gate Level
- Analog BIST Simulations
Post Silicon Debug and ATE Support
- Post Silicon Support and ATE Bring up
- ATE Board Design and Bring up
- Test Program Development and Testing in different types of testers like Advantest 93K and Production support
DFT Flow
The in-house DFT flow for SCAN, OCC, Compression, ATPG, MBIST and JTAG implementation & Simulations transforms the tedious hindsight to an eased up and cost-productive quality affirmation methodologies.
Foundation IP Design & Automation
IP Design & CAD
- Circuit Design & Char
- High Speed & Power Management Analog IPs
- PLL/LVDS/LDO/Bandgap Design
- I/O Libraries Design & Characterization
- Std Cell Characterization
- Automation Flow Development using EDA tools,
- Python/Perl/Tcl Scripting
Layout Design
- Process and Layout Migration
- Custom Memory and Memory Compiler
- Analog Layout Design
- I/O Libraries, RF, Serdes Layout
- Std Cell Library Development
- Process and Layout Migration
- Physical Verification for DRC/LVS/PERC
IP Design & Layout Flow
s per the specifications, firstly an ad-hoc design is deliberated. And then after a pre-simulation check, related schematic tests are conducted before the final physical verifications and electrical signoffs.
Embedded System Solutions
We provide end-to-end embedded software development services like firmware, BSP, middleware, Linux, device drivers, and bootloader development; hardware design services like multilayer PCB and FPGA-based hardware design. Our dedicated and proficient team has vast experience directing architectures for both ARM & X86. Additionally, it is acknowledged for working with various microcontrollers. The team assures reliability and quality while delivering Embedded System Design services for Storage, Automotive, Networking, and Consumer applications. I2Labs TechSoft majorly aims to decode this complex software and hardware technology amalgam to deliver robust, high-performance, and innovative products thus helping you gain a significant competitive advantage.
Post Silicon Validation & Emulation
Functional Validation
- Requirement Analysis
- Validation Plan Development
- Test Suite Development
- Test Environment Automation
- Board Bring-up
- IP/SOC Level Validation
- Processor Validation
- Low Speed Peripherals
- High Speed Peripherals
- 4G/5G Modem Validation
- Firmware Development
- Firmware Validation
Characterization
- Digital Characterization
- Analog Characterization
- Jitter Measurements
- Eye Diagrams
- Waveform Validation
- Waveform Validation
- ATE Measurements
- Test Automation
System Performance
- PVT Characterization
- Power Validation
- Compliance Testing
- Interoperability Testing
- Test Automation
- Benchmark Testing
- Stress Testing
- Stability Testing
- HW/SW Subsystem Testing
- OS-wise System Performance Testing
System Debug
- Board Bring-up
- Resolve System Boot Issues w.r.t Specific Chipset/Platform
- Resolve Linux Related Issues on Specific Chipset/Platform
- Analyze Crash Issues
- Analyze Core Dump
- Fix Memory Leaks
- Identify Cache Issues
Emulation
- Emulation, Validation & Prototyping on FPGA & Processor-Based Platforms
- Board Bring-up & Device Planning
- Design Partitioning, Integration, IO & Memory Handling
- Implementation & Timing Closure
- Configuration & Hardware Debug
Post Silicon Validation Expertise
Domains
- Mobile
- Automotive
- Wireless
- Mutlimedia
- Connectivity
- IOT
- Ethernet
- Storage
- Networking
IPs/Technology
- PU cores- ARM, X-86, PowerPC, Tensilica
- DDR 4 / 3 / 2
- USB2.0, USB3.0, OTG
- PCIE 1 / 2 / 3 / 4
- Ethernet – RGMII, SGMII, QSGMII
- SATA 1.0/2.0/3.0
- SDIO
- MIPI – DSI, MIPI- CSI
- WLAN 802.11 a/b/p/g
- H264 Decoders
- SPI, UART, I2C, I2X,CAN,LIN
- AXI, AHB, APB
- PLLs, ADC, LCO, PMU
Tools & Automation
- C, C++, Embedded C, Visual Studio
- CMM, Python, PERL & Labview, Tcl
- Various Logic Analysers
- USB, SATA Protocol Analysers
- Oscilloscope – DPO71254C, with 4 trimode differential channels
- Votsch Thermal chamber
- DDR Analysis Software.
- FPGA platforms – Altera. Xilinx
- Emulators – Veloce, Zebu, Palladium
- Debugger – Trace 32, RVDS
Emulation Expertise
Platforms
- Processors- ARM, X86, Tensilica, Microblaze, Picoblaze
- Boards- Altera, xilinx based multi-FPGA boards
- Emulators – Zebu, Veloce & Palladium
Interfaces
- AXI, AHB, APB, PLB
- PCIE, SATA, DDR
- MAC, USB
- SDIO
- MIPI – DSI, MIPI- CSI
- WLAN 802.11 a/b/p/g
- H264 Decoders
- CAN , I2C, SPI, UART
- DMA, CRYPTO, PRNG
Tools
- Synthesis Tools – Xilinx Vivado, Xilinx ISE, Altera Quartus, Mentor Precision, Cadence Quiclturn
- Partition Tools – Synopsis Certify
- Simulation- Modelsim, Questasim, Cadence NCSim & Quickturn
- System Debug – ARM realview ICE, Xilinx chipscope, Altera signaltap, Synopsis Identify, Debussy, J-Link, Trace-32